RFEL awarded further phase of Osborne programme for Dstl
RFEL has been awarded a further phase of the Osborne programme for Defence Science and Technology Laboratory (Dstl), Porton Down, UK.
The Osborne programme provides DSTL with the capability to conduct Electronic Warfare (EW) Systems development using Model-Based Design. This approach allows users to develop candidate systems using COTS modelling tools, such as MATLAB and SIMULINK and to realise them with FPGA vendor's Synthesis and Place and Route tools.
This approach rapidly reduces the cycle time for developing, synthesising, trialling and verifying candidate solutions, which is a cardinal requirement for the programme. This allows the Authority to use familiar tools and existing design work and provides access to a wide range of FPGA and SOC implementation options.
The Osborne Development Environment (ODE) couples effective simulation models, which are optimised for simulation speed, with effective synthesis models, which are optimised for FPGA implementation. The coupling of these two entities allows the user to switch seamlessly between synthetic and real-world implementations with the end goal of this being available on a component-by-component basis. The models share a common parameter set, effectively passing the designed detail from the design to the realisation. The whole design process is supported with detailed Workflow Flow management and has integrated Security Management.
Alex Kuhrt, RFEL's CEO said: "DSTL's Osborne Programme has drawn on RFEL's core skillset and our in-house design philosophy of Model-Based Design. All our commercial IP cores are fully bit-true modelled as part of our Paradigm Work Flow. The Osborne Programme is exporting this approach to meet our customer's complex requirements. The programme will deliver a comprehensive suite of tools and hardware that will give DSTL designers a real advantage over the native toolsets. With DSTL's support, we hope to offer these tools as a packaged suite to FPGA designers everywhere very soon."
A range of hardware platforms will be provided for DSTL to suit a wide range of applications, again using COTS technologies and stable industry standards. Crucially, the hardware feature-set is reverse engineered and represented in the ODE. This important step means that the designers are free to develop solutions, knowing they will correctly partition and utilise the available features of the final hardware platform.
Ben Egan, DSTL's Technical Lead said, "The programme is scheduled to deliver the Initial Operating Capability to DSTL in late 2017 with extensive future support and development beyond that. These tools will support DSTL's wider aims of increasing capability whilst reducing costs and ensuring appropriate scientific rigour."